1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method of verifying a layout pattern.
2. Description of the Prior Art
Photolithography and etching technologies are frequently used in semiconductor manufacturing. The photolithography technology usually involves transferring a complicated integrated circuit pattern to a semiconductor wafer surface for etching. These patterns must be extremely accurate for forming delicate integrated circuits. In the photolithographic step, deviations occur and jeopardize the performance of the semiconductor device when the patterns on the reticles are transferred onto the wafer surface. Such deviations are usually related with the characters of the patterns to be transferred, the topology of the wafer and various process parameters. There are many known compensations for the deviations caused by the optical proximity effect to improve the image quality after transfer. The known method is called “optical proximity correction, OPC.” The commercial available OPC software repairs the layout patterns on the reticles using the theoretical image to obtain the correct image patterns on the wafer.
FIG. 1 is a flow chart illustrating the verification of the layout patterns on the reticles using OPC by the conventional techniques. First, in step 102 inputting a layout pattern is performed. Then in step 103 the Boolean pre-treatment of OPC is performed on the layout pattern to obtain a preliminary layout pattern. Afterwards in step 104 the OPC is performed to correct any particular pattern. Later, the process rule check, PRC, in step 106 and the lithography rule check, LRC, in step 108 are separately performed. Then the error screening and check in step 110 is performed. If the obtained patterns are correct and usable, the patterns are output (step 112). If incorrect, the pattern correction in step 114 is performed and the patterns are output if no error is found.
FIG. 2 is the flow chart illustrating the LRC check of step 108. First, in step 116 perform the OPC correction on the layout patterns according to the model information. The layout pattern undergoes the step 118, i.e. simulating the pattern at the best image plane of a photoresist layer resulting from a best focus exposure. The “best focus” is generally located at the half way of the thickness of the photoresist layer. The “best image plane” is referred to an image plane at the same level of the best focus on the photoresist layer resulting from the best focus exposure and a corresponding development. Afterwards, the LRC of step 120 is performed. If the image patterns are correct and usable, the layout patterns are output (in step 122). If incorrect, the OPC in step 116 is performed. Accordingly, problems such as pinch, bridge, and critical dimension uniformity are detected and the layout patterns are corrected.
However, in addition to the problems such as pinch, bridge, critical dimension uniformity, and the like, pattern collapse due to undercut or film loss frequently occurs if defocus happens. They are serious 3-Dimensional configuration defects of the photoresist patterns. FIG. 3 illustrates a schematic cross-sectional view of a simulated image of a photoresist layer resulting from a best focus exposure. Because the current LRC method can only simulate the image at the best exposure plane, i.e. the image of plane b, the possible pattern defects at the top plane a or at the bottom plane c are not able to be found if the exposure is defocused.
The quality of the layout pattern is embodied by the film pattern after etching. However, simulation of the film of the pattern after etching to verify the layout pattern of the mask has never been brought forward.
Hence, there is still a need of a better method for verifying a pattern layout for confirming the layout pattern on the reticles.